LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY iic001 IS

 PORT
 (
  clk   : IN  STD_LOGIC;                                        
  start  : IN  STD_LOGIC;                                        
  restart  : IN  STD_LOGIC;                                        
  data  : INOUT  STD_LOGIC_VECTOR(7 DOWNTO 0);                                        
  inoutda  : BUFFER STD_LOGIC;                                        
  busy  : OUT  STD_LOGIC;                                        
  scl   : INOUT  STD_LOGIC;                                                             
  sda   : INOUT  STD_LOGIC;
  continue   : OUT  STD_LOGIC
 );
 
END iic001;

ARCHITECTURE jet OF iic001 IS

 SIGNAL i : integer range 0 TO 32 := 0 ;--step status word

BEGIN

 p0:process(clk,start,restart)
 variable j : integer range 0 TO 8 := 0 ;
 variable data_signal : STD_LOGIC_VECTOR(7 DOWNTO 0);
 begin
  if clk'EVENT AND clk = '1' then
  
   if inoutda = '1' then--data input enable
    data <= (others => 'Z');
   end if;
   
   if i = 0 then                      
    inoutda <= '1';--init
     if start = '0' then
     scl <= 'Z';
     sda <= 'Z';
     busy <= '0';
     continue <= '0';
    else           --start
     scl <= 'Z';
     sda <= '0';
     i <= 1;
     busy <= '1';
     data_signal := data;
    end if; 
   end if;
   
   if i = 1 then--address and read or write status
    scl <= '0';     
    i <= 2;
   end if;

   if i = 2 then
    scl <= '0';
    if j <= 7 then
     sda <= data_signal(7-j);
     j := j+1;
    end if;
    i <= 3;
   end if;
   
   if i = 3 then
    scl <= 'Z';
    i <= 4;
   end if;
    
   if i = 4 then
    scl <= '0';
    if j = 8 then
     j := 0;
     i <= 5;
    else
     i <= 2;
    end if;
   end if;   

   if i = 5 then
    sda <= 'Z';
    i <= 6;      
   end if;
   
   if i = 6 then
    scl <= 'Z';
    i <= 7;
   end if;
   
   if i = 7 then--slave react
    scl <= '0';
    if sda = '0' then
     if data_signal(0) = '1' then
      i <= 8;--choose read process
     else
      i <= 31;--choose write process
     end if;
    else
     i <= 0;
    end if;
   end if;
   
   if i = 8 then--read process
    i <= 9;
   end if;
   
   if i = 9 then
    scl <= 'Z';
    i <= 10;
    inoutda <= '1';
    continue <= '1';
   end if;
   
   if i = 10 then
    scl <= '0';
    if j <= 7 then
     data_signal(7-j):= sda;
     j := j+1;
    end if;
    if j = 8 then
     j := 0;
     i <= 12;
     inoutda <= '0';
     data <= data_signal;
    else
     i <= 11;
    end if;
   end if;
   
   if i = 11 then
    i <= 9;
   end if;

   if i = 12 then
    if start = '1' then
     sda <= '0';
     i <= 13;--choose continue read
     continue <= '0';
    else
     i <= 32;--choose end
     sda <= '0';
    end if;
   end if;

   if i = 13 then--continue read
    scl <= 'Z';
    i <= 14;
   end if;
   
   if i = 14 then
    scl <= '0';
    i <= 15;
   end if;
   
   if i = 15 then
    sda <='Z';
    i <= 9;
   end if;
   
   if i = 32 then--end
    scl <= 'Z';
    i <= 0;
   end if;

   
   
   
   
   
     
  end if;  
 
 
 end process p0;
 
 
 
END jet;